How to simulate Bandwidth and Phase Margin of a PLL

[chenliy]

I am designing a 400-800MHz PLL. I have calculated Bandwidth and Phase Margin of the PLL. But I donot know how to understand Bandwidth and Phase Margin of PLL. Is it as same as Bandwidth and Phase Margin of op amp? How can I simulate Bandwidth and Phase Margin of a PLL?

 

[paladinzlp]

You can simulate the Bandwidth and phase margin
using matlab.
I hope that helps.

 

[sutapanaki]

BW and PM in a PLL has, of course, the same meaning as in any feedback system, including opamps working in a feedback configuration.
As for the simulation of it, you can use simulink, you can also use spice. All you have to do is create real models for the blocks in your loop, accounting for all significant poles and zeroes. Then linearize the system with these models and simulate.
Alternatively, you can do a step transient responce, inserting into the loop a step disturbance and looking at how it settles. You can then make your conclusions about stability.

 

[chenliy]

Can i use Cadence's tools simulate Bandwidth and Phase Margin of a PLL?How can I do it?

 

[yibinhsieh]

Dear chenliy:

Can i use Cadence's tools simulate Bandwidth and Phase Margin of a PLL?How can I do it?

You can't. You can just use the behavior model to simulate the Bandwidth and Phase Margin for PLL. Like S-domain model.

Yibin.

 

[amarnath]

hwy dont u just oplot the frequency response of the loop filter ur using...from that u can calculate the BW.

regards
amarnath

 

[sutapanaki]

Actually, just the frequency response of the loop filter is not usually enough. The VCO has another pole, besides the usual 1/s. Then if you have something between the charge pump/filter and the vco (V-I converter for example) its frequency response will have to be taken into account too. You can think those secondary effects are at high frequencies, but according to Murphy they get in the picture exactly when you don't want them. Plus, if the reference to the pll is from a crystal oscillator, it is usually low-jitter and then one would want to enlarge the bandwith to try and cancel more noise from the supply - consequently the secondary effects come into picture with full force.
In Cadence you can do pole-zero analysis of your circuit blocks. This is enough to create a good model for the system. Then you can simulate the model in Cadence or Simulink or whatever, even Pspice will do. The key is to make good models.

 

[khouly]

try this model
u can use them to check stabilty , bandwidth

 

[Btrend]

the loop formed by PLL and OPamp are different in nature,
first of all, loop in OPamp (commonly is negative feedback) is continuous time, that is the loop is "always" there.
secondly, the loop in PLL is not "always" exist, it only exist in part of PFD cycle.
so the loop is not continuous, it was said as "sample-data loop" and is not continuous loop. If you want to know the exact behavior of the loop , you need to do Z-domain analysis.
finally, from the above 2 point of view, the usual loop concept using in OPamp is only a approximated version of the actual sample-data loop, this should be keep in mind . Otherwise, you will find a weird thing, why the loop gain > 0 and the phase is -180° which should be oscillated at a usual Opamp negative feedback loop.

 

[sutapanaki]

That is generally true. The loop is indeed sampled in time. But as you know in lock and when the input frequency is let's say 10-20 times bigger than the loop bandwidth one can use continuous time approximation which is good enough. Simply said, the filter capacitor doesn't have time to discharge a lot for the period of the input clock. Things start breaking down when the input frequency gets very close to the loop BW.
The best of course is to do transient analysis with introducing some step disturbance in the loop and watching how it settles. But doing small signal stability analysis first is perfectly legitimate too, when you know what you're doing. Z transform is also a thing to be considered.

 

[layes2]

simulate it use matlab
or verilogA in linear model

 

[Yun Lin]

Yes. You can use matlab. The bandwith will effect the lock time.

 

[layes2]

use matlab pll is a 3rd system
or 4th
easy to do

 

[rambus_ddr]

you can use verilog_A to write pll model and use spectre to simulate.

Can i use Cadence's tools simulate Bandwidth and Phase Margin of a PLL?How can I do it?

 

[option318]

Thanks, khouly offer work_116 model.

 

[buckaroo]

the loop formed by PLL and OPamp are different in nature,
first of all, loop in OPamp (commonly is negative feedback) is continuous time, that is the loop is "always" there.
secondly, the loop in PLL is not "always" exist, it only exist in part of PFD cycle.
so the loop is not continuous, it was said as "sample-data loop" and is not continuous loop. If you want to know the exact behavior of the loop , you need to do Z-domain analysis.
finally, from the above 2 point of view, the usual loop concept using in OPamp is only a approximated version of the actual sample-data loop, this should be keep in mind . Otherwise, you will find a weird thing, why the loop gain > 0 and the phase is -180° which should be oscillated at a usual Opamp negative feedback loop.

very good!

 

[gavin168]

After open the PLL_2 in the work_116 khouly upload, then how to do the PM simulation? It is said LTI viewer should be used? but i do not know how to complete it?

Thank you

Thanks, khouly offer work_116 model.