How to simulate an analog module of ADC in Verilog AMS?

[brenox]

verilog ams testbench

Hi, my name is Breno and I am from Brazil, so I apologize about my English.
I am studying verilog AMS to implement an Analog to Digital Converter. My doubt is about how can I simulate an analog module? I tried to simulate some examples given in the page https://www.designers-guide.org/VerilogAMS/ but I only could simulate the examples with digital blocks running the script, because they come with the top module with the extension .vams and the testbench in .vams, or both in .v extension. But when I tried simulating an analog module, they come with the top module in .vams and the testbench in .scs extension. And the script is just “#!/bin/sh; spectre testbench.scs”. My question is:
- How can I simulate an analog module? Is it with the testbench in .scs?
- What is the script for doing the simulation? Is just the “spectre testbench.scs”? This command “spectre” is not recognize by the cadence simulator.
- Could you send me an example of an analog module with testbench, script and some prints of the waves resulted of the simulation?
- Can I make testbench in extension .vams for analog modules?
- Where can I find more about making verilog AMS testbenchs?

Since now, I appreciate. Thanks.

Breno

 

[bigworm]

verilog-ams examples

if you have both scs and vams, you can try ade with using ams as simulator
which does work.

as for your question, to simualte in command line, I only have experience in using scs only nestlist. the script is like " spectre -arguments *.scs"