Ken,
To simulate mismatch in all devices of the circuit I normally use the DCmatch analysis of HSpice. I've been designing a D/A myself and this analysis has helped me very much to evaluate the mismatch in my circuit.
In HSpice, the mismatch is defined in a block in the netlist called "variation block". In this block you can define the mismatch model for all transistor parameters that you like, and also for resistor and capacitor elements.
Here's an example of this block, directly from the HSpice manual:
.variation
.global_variation
nmos MODN vth0=0.07 u0=10 %
pmos MODP vth0=0.08 u0=8 %
.end_global_variation
.local_variation
nmos MODN vth0='9.5e-9/sqrt(get_E(W)*get_E(L)*get_E(M))'
+ u0='0.7e-6/sqrt(get_E(W)*get_E(L)*get_E(M))' %
pmos MODP vth0='14.5e-9/sqrt(get_E(W)*get_E(L)*get_E(M))'
+ u0='1.0e-6/sqrt(get_E(W)*get_E(L)*get_E(M))' %
.element_variation
R r=10 %
.end_element_variation
.end_local_variation
.end_variation
Hope this helps you,
Leo.