How to show the connectivity for layout using cadence

[bluesy]

Hi,
I am new to layout design especially using Cadence. How can i do so that it can show the connectivity between the transistors using cadence? :???::???:
The layout for each transistor that i have inserted is very complicated for me and i don't know which is drain, source and others. I dont really know how to make routing between them .There are many boxes and i dont know how to differentiate them. May i know where can i search for the info?
Does anybody can help me?? Thank you so much for your help

 

[steadymind]

layout is not complicated. it is simple shapes and different layers that make a device. to know about the layers and the rules you need to refer the pdk. to retain connectivity you can start naming the paths with net names. if your cadence setup has layout xl then it retains connectivity information.

which cadence version are you using?

 

[muffassir]

in layout window there is option of workspace select there as Basic a new window pops up in the left corner as NAVIGATOR...from there you can see your devices as NM0 or else as u named them and also the nets/pins etc. Just select the device that you want to view it will get highlighted in the layout window.

To see which drain is connected to what ...go to connectivity>nets>show allconnected nets ...click on it then select the pin or mos to see the connection of it with the other ...

Hope it will help you...if u need more info then write here..Also do provide the version you are using..Above all is for the IC 6.1.4.500 cadence and virtuoso XL/L

 

[bluesy]

Thank you so much,i am using version if not mistaken. May i know that if i have to add some dummy transistors for matching purpose in the layout, should i add the dummy transistors on the schematic part? If yes,how should i make the connection for them and do the sizing?

---------- Post added at 11:17 ---------- Previous post was at 11:12 ----------

how can i view pdk.? thanks. i clicked connectivity n then there is no net for me to choose,it only can choose like define pin, propagates nets ad shape to net , mark net, unmark net,assign net or others.

 

[steadymind]

version?
you need to add dummies to schematic as well. if you are shorting the gate, drain, source of dummies in layout to vss, do the same on schematic

 

[bluesy]

version 5, thanks but then is that the sizing of dummies same like other transistors as well?

 

[steadymind]

version 5 doesnt have. a lot of connectivity features. i size my dummies with
width as the device to match,but give it minimum length.

 

[bluesy]

is that i cant refer the pdk. to retain connectivity? i used layout XL to insert transistors by picking from schematic also. Thank you so much for your informations.