How to set_false_path to entire module?

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hung2000

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Hi,

I am working on next version of a top module. This top module has instantiated a sub-module which will eventually go away. How can I exclude timing of this entire module?

Currently I am doing this:

set_false_path -thr [get_pins INST_0/*]
set_false_path -thr [get_pins INST_0/*/*]
... [to the deepest level]
set_false_path -thr [get_pins INST_0/*/*/*/*/*/*/*/*/*]

Is there any easier way doing it? This sub-module has multiple clocks going into it (to be disconnected in next version).

Many thanksssss!

Gary
 

i think that get_pins should retrieve the entire port list of module INST_0 so i don't know why you have difficulties with it.
 

I think one easy way maybe, wirte a RTL wrapper for that sub-module.
Just define the input/output and assign all the outputs to a constant value. Then, your problem will gone at both simulation and synthesis.
 

OhaAmo said:
i think that get_pins should retrieve the entire port list of module INST_0 so i don't know why you have difficulties with it.
Click to expand...

because there are still large number of internal paths within INST_0 being analysed and reported. I just want to get rid of them in my timing reports.

- - - Updated - - -

asic_service said:
I think one easy way maybe, wirte a RTL wrapper for that sub-module.
Just define the input/output and assign all the outputs to a constant value. Then, your problem will gone at both simulation and synthesis.
Click to expand...

This is just a quick STA pre-study without changing current RTL (this module will go away eventually anyway). I am just wondering if there is easy constraints to disable all internal/external timing paths of this module.
 

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