how to set up a delay using two clock's

[zbarabas]

I'm struggling to design the following in vhdl:
-when an event occurs (rising-edge) set "A" to 0 then after 1000 clock cycles if no event occurred, set "A" to 1.
More exactly: I made a stepper controller which has 2 motor current settings.
When step pulses are coming I want to use a higher current. When are no pulses for 2 seconds (let's say 1000 clock cycles) set a lower current.
Can anyone guide me with an example?

 

[shaiko]

Sounds like something that can easily be implemented with the simplest of state machines...

 

[zbarabas]

Thanks shaiko, can you please present an example?

 

[shaiko]

1.Do you know VHDL/Verilog ?
2.Do you understand the concept of a Finite State Machine ?