Right. Here's something that actually does something, so maybe that makes it a bit clearer...
Code:
module test_counter (
input clk,
output reg [7:0] count
);
initial begin
count = 0;
end
always @(posedge clk) begin
count <= count + 1'b1;
end
endmodule // test_counter
Now you see that the "initial" statement is used
only to provide the register with a initial value. In the case of an fpga implementation that means the state of the flip-flop right after the configuration bitstream has been loaded, and before the global set/reset deasserts the reset.
Essentially it does 2 things. 1) make sure you know what state your physical hardware actually starts out with. 2) make sure you know what your simulation starts out with. And as you may find out, it is rather important to have simulation be as close as possible to what your actual hardware is going to do.
If for example you don't specify the initial state of the flip-flop, the actual hardware will start out with the flip-flops set at 0. So no problem there. In simulation however the simulation engine is of the opinion that "count" is undefined at t=0.
And since "undefined" + 1 is still undefined, this module would be a little disappointing if you neglected to specify the initial conditions.
Hope that clears things up somewhat...