hi, i'm new with vhdl coding (one week experience).
how to separate a string of data into even and odd data?
is it the same as c language or there are any better ways?
what is the condition on which you want separate the two data streams?
e.g. if you want to separate them on each clock edge...
you can have a bit counter (a T flop) and use its output as select line to a 2:1 multiplexer. At every odd transition you can separate the data.
else just connect your signal generated to produce your condition to the select line of the mux.
while learning a HDL It is a good practice to have an idea of the hardware which is going to be synthesized because of your code.Once you know the hardware..coding is a piece of cake.you can refer to any text book on VHDl.(I don't want to spoil your learning experience)
Happy coding.