The choice of cells for clock tree is usually done according to the following
a) Balance of the rise/fall times of the inverters/buffers. If there is imbalance(determined by the tool), the tool rejects that cell.
b) The decision on buffer vs inverters was debate in older technologies....the newer technologies it is inverters.
c) inverters will be chosen by the tool because the new technologies(20nm,16nm....) .....
........ Nowadays it is not an important question anymore.... inverters+ tool decisions(cadence/synopsys) are smart enough to do the job