How to Select Foundry

[Raptor]

getting orders for foundry

If you were to choose/select a foundry for a particular project what prameters would you look at?
More from a technical point of view than cost?

 

[modelsim62c]

how to select a foundry

"How to select a foundry (for standard-cell ASIC)?" To answer this question satisfactorily, you'll need to know a lot of details about your project. On the technical side, does it have mixed-signal (analog) components, like special I/O requirements, PLLs, ADC/DAC converter modules, R/F? Or is it a run-of-the-mill digital design described completely in an HDL (VHDL or Verilog)?

If your planned design will require significant 'custom' or analog/mixed-signal blocks, and you plan on designing them in-house, then you'll obviously need a foundry to provide you with a process design kit (PDK.) All the pure-play foundries (SMIC, Chartered, TSMC, UMC) are willing to provide adequate PDKs, to qualified customers. There are other foundries (not pure-play), which emphasize 'turn-key' services. They are less likely to give you a complete/satisfactory PDK, so advanced analog/mixed-signal stuff is probably not feasible to do with them.

And what about project volume and product lifecycle? A limited quantity production (less than 1000 wafers) will have a much higher marginal-cost (cost per unit) than a huge order. What this means for you, is that a design with small manufacturing quantity may not be suitable for a full ASIC production run. There are some ASIC vendors or solution partners which take orders for just this situation. Using such a service, whether its offered by the foundry itself or through a third-party partner, is generally cheaper than fabbing direct on a foundry's full-production line.) For a huge volume order, you'll want to deal direct with the foundry, obviously.

Well now, let's say you have the Verilog/VHDL RTL for your digital design. But do you know what to do next? Will you need help with place&route, design-for-test (DFT), clock-tree, DRC/LVS? In other words, do you need 'back end' help, or is your company setup to handle this in-house? Here's the 'tool-flow' question -- do you own your own front-to-back end tools, or not? And here's where it gets confusing. In the ASIC industry (by 'ASIC industry', I mean the business of manufacturing chips for fabless companies), marketing uses two terms to describe the customer's tool-flow: 'COT' or 'ASIC'
COT means 'customer-owned-tooling', and as you might guess, this means YOU handle all back-end activities on your own. Whether you do that inside your company or subcontract to another design services shop (like easic, esilicon, etc.), is up to you -- all your FOUNDRY cares about is a complete, rule-checked GDSII file, because the GDSII is the only thing they accept from you (along with the production order paperwork.)
The other tool-flow, simply called ASIC, means the foundry itself does the backend work for its customer. You handoff a synthesized-netlist (from Design Compiler), some timing-constraints, and other 'physical design assets' (like the PAD-ring order, pin-package assignment, etc.), the foundry runs backend on your netlist (floorplan, DFT, place&route, CTS, DRC/LVS) -- they do the rest. At some point, they send back a 'postroute' netlist and SDF-file (timing annotation) -- you run your gate-level simulations on the postroute-netlist/SDF (you DID plan for gate-sims, right?) If its good, then you sign-off the release-to-manufacturing form. If not, you tell the foundry what's wrong, and they try to fix it (hope you don't have to do this.)

Advice: Experienced IC companies (like NVidia, ATI, Broadcom) do the COT-flow. They have the expertise, manpower, and high-volume (ASIC) products to justify buying all their own EDA-tools (they're expensive...) They pay milliions for those tool-licenses, but save a bundle because they can go direct to TSMC/UMC/SMIC/Chartered, with a ready-to-go GDSII file.

For the same quantity order, the ASIC tool-flow (not COT) is more expensive AND slower. When you handoff the initial (non-placed) netlist & constraints, the foundry must take time to run backend. Most foundries are pretty slow at this (2-3 months or more is common. With COT, if you partitioned the design good, know the tools-capacity, and avoid timing/congestion/SI bottlenecks, you can turn the backend in 3 weeks or less.)

COT tool-flows work best with the pure-play foundries (UMC/TSMC/SMIC/Chartered), and taking this route gets you the best 'price per wafer.' As a matter of fact, most pure-plays won't do ASIC-flow (not directly anyway, maybe through a service partner.) The one thing to watch out for is packaging/testing and mask-order. The typical digital-logic ASIC maskset is a fixed NRE cost that YOU must incur -- for 65nm, it's about $1.3 million USD. For 130nm, I think it's downto about $500K USD. (For dedicated mixed-signal, high-speed, extra metal-layers, or other exotic process variations, price goes up from here...) Anyway, the NRE is a huge fixed cost, and it's the same $$$ cost whether you fab 1 wafer, or 1000000 wafers. (By the way, foundry will laugh at you if you tell them you plan on fabbing just 1 wafer.)

Sorry, this is a bit out of order. Going back to the ASIC-flow, why pick the ASIC flow? Well, backend tools are expensive, difficult to operate, and most importantly, maybe your company doesn't do enough tapeouts to justify that expense. They also handle manufacturing testing (after the wafers are fabbed), chip-packaging and assembly, all for you. On top of that, for limited production runs, the ASIC-flow can in fact be cheaper, depending on the contract arrangement. The fabs offering ASIC-flow generally have a nice IP portfolio -- everything from high-speed PLLs, to PAD cell (I/O libraries) for SATA, PCI-e & DDR1/2/3, and possibly complete, proven functional-blocks (SATA, Fibre-channel, GbE transceiver, etc.) For example, LSI Logic (the merchant foundry division) secured a lot of ASIC-flow business from host bus-adapter companies Qlogic & Emulex, because LSI had Fibre-Channel and other high-speed serial IP before anyone else. (Too bad they pissed everyone off by entering the HBA/RAID adapter market -- nothing alienates foundry customers more than entering their market and selling competing products!) Samsung offers ARM7/9/11 much, much cheaper any of the pure-play foundries (when comparing the upfront one-time license cost -- recurring royalty payments are probably comparable.) Getting back to my main point, "ASIC-flow" foundries charge a premium (compared to COT-flow foundries) because of the "value added service -- backend service, testing/assembly, larger or better-proven IP-portfolio.

General rules of thumb to remember:

Foundry process "quality" (i.e. process maturity/stability over time, past track record) varies from fab to fab. TSMC is generally regarded as outstanding (first class.) The 'cheaper' foundries (SMIC, Chartered) have much larger process variation (and higher D0 defect rate.) The best analogy I can say is, "+/- 5% tolerance resistors for $10, or 10% tolerance resistors for $6." Since the pure-plays bill on a 'per wafer' basis (whether the wafer tests as working or not), it's the customer's responsibility to deal with defects (either by building redundancy into the design or slowing the clock down in case of slow parts.)

The ASIC-flow foundries generally arrange deliverable terms @ 'fixed price per KGD' (known good die). So at least you know up front, exactly how much usable product you're getting, at what price.

For very small production orders, some foundries offer multi-project wafer. TSMC calls it 'cybershuttle' Instead of ordering a full wafer (and mask-set for a full wafer), you get a 3mm x 3mm section on a wafer, shared by many other customers. Every 1 or 2 months, TSMC kicks off a Cybershuttle run (with the shared wafer), so for about $100K-$200K USD, you get back 100 or so individual dies. (You're still responsible for testing & packaging. ) This is good for prototyping small projects.

It's getting late, but I hope I answered something useful.