How to run frequency response simulation for inductance peaking in cadence?

[usuikazkou]

How to do frequency response simulation for inductor peaking in cadence?
I want to design current mode logic with inductor peaking, from the textbook I know that I should run frequency response for it to choose the inductor value, but how to do the simulation?
Best regards.

 

[erikl]

Run ac simulation.

 

[usuikazkou]

with vdd =1v. how should I set the testbench?
below is my schematic
thanks.

 

[erikl]

vdd =1v. how should I set the testbench?

Something like this: