How to run frequency response simulation for inductance peaking in cadence?

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How to do frequency response simulation for inductor peaking in cadence?
I want to design current mode logic with inductor peaking, from the textbook I know that I should run frequency response for it to choose the inductor value, but how to do the simulation?
Best regards.
 

with vdd =1v. how should I set the testbench?
below is my schematic
thanks.
 

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