How to resolve a large odd harmonics issue in ADC?

[waiwai]

I am designing a 10bit pipeline ADC. The schematic simulation shows that the odd harmonics are too large(especially,the third harmonic is 55dB).
Can anybody give me some suggestion on how to find the reason?
Thanks.

 

[renwl]

Re: help for ADC design

make sure the settling time is enough

 

[wdd]

Re: help for ADC design

I am designing a 10bit pipeline ADC. The schematic simulation shows that the odd harmonics are too large(especially,the third harmonic is 55dB).
Can anybody give me some suggestion on how to find the reason?
Thanks.

sampling swith
opamp (settling time)
reference (settling time)

 

[manissri]

Re: help for ADC design

the bandwidht and settling time should be enough and make sure that there is no doublet in ur frequency response

 

[basunaik]

Re: help for ADC design

I am designing a 10bit pipeline ADC. The schematic simulation shows that the odd harmonics are too large(especially,the third harmonic is 55dB).
Can anybody give me some suggestion on how to find the reason?
Thanks.

May be u can check with the analog input itself which may include the harmonics. If u r supplying with the harmonics there is no way u can suppress it in the ADC. Try to filter out all the harmonic present in the input.
Regards,
basu

 

[selina_wch]

help for ADC design

I also have a question. I think the reason why setting time will lead to harmonic is that it has fixed periodic error. Is it right?

 

[mince]

help for ADC design

Make sure Fsample/Fsignal is not an integer otherwise your quantization noise will be periodic and will introduce errors in the spectrum.

 

[melc]

Re: help for ADC design

I've read strange advices here. If he is *designing* an ADC and not *using* a pipeline ADC into an application than he can't filter any harmonic at the input (this could be antialising ?) because it's killing the analogic bandwidth. Fsample/Fsignal could be any (integer or not) as long Nyquist criteria is OK, you can't restrict even the simulation because the Fsignal is unknown and unpredictable.

I'm curious what reason he found for this behaviour and how he solved the problem.

thx,

 

[Karthikeya]

Re: help for ADC design

Hi,
melc, for your kind information please refer this site which gives the procedure to find the harmonic distortion. If you go by this calculation, sampling frequency cannot be integer multiple of input frequency. This is a standard procedure followed.

**broken link removed**
regards