how to replace simulation based delay in VHDL to make code synthesizable

[AmmaraYasmin]

i have made a block of OFDM in xilinx system generator which contains few delays then i translated the code in VHDL using the option in system generator. but that vhdl code contains delays that is made with after statement which is not synthesizable.

i have to run that code on extreme dsp kit but i am helpless.

is there any option to replace that delay code.
in my mode it is written in this way
d=q after 200 ps

i need a code to replace this delay code

 

[std_match]

Can you explain why you need the delays?
200 ps is too short to implement with a sequential circuit.
You can do short delays by routing the signal thru an extra LUT or by separating the source and destination a certain distance on the chip.
The precision will not be good, so it is better if you can do the design without the delays.

 

[AmmaraYasmin]

Delays are requirement of my design.... i need the synthesizable code. even i increased the delay but it gives timed out error on the hardware.

what is LUT.... actually i am new to VHDL and unable to nderstand all that too fast and time is short....

kindly come up with code if u can ..........

thanks in advance

---------- Post added at 01:19 ---------- Previous post was at 01:17 ----------

do u mean loop up table.........?

 

[kalyanasv]

use a BUFD element: You should find it in your library for the paritiuclar device you are using for e.g. Spartan 3C or Virtex...etc.
You a for loop with a generate and create as many buffers components as you want.
Or simply repeat the component "n" time till you get your required delay in post layout sim

 

[BlackHelicopter]

Depending on your target device you may be able to instantiate an I/O Delay primitive. Have a look through the vendors documentation to see if your FPGA has the capability. If so, they will typically provide example VHDL/Verilog code of how to instantiate the components.

 

[AmmaraYasmin]

in our code BUFT is used, is that sumthing related to BUFD....we are using Extreme development kit Virtex IV ....what should be the solution for that

---------- Post added at 06:59 ---------- Previous post was at 06:57 ----------

Blackhelicopter i didnt get what you are saying....can u explain with
example