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# How to remove this WARNINGs

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#### sheikh

Hello Dears
could you please tell me how can i remove these warnings? I didn't have any idea for using latches also I have not any incomplete "Case" or "if" statement!! ( maybe i cant recognize all conditions!!)
Code:
architecture state_machine of YCbCr_Controller_Pipeline is
TYPE TYPE_STATE is (RESET, T0, T1, T2, T3, T4, T5, T6, FINISH);

signal next_state    : TYPE_STATE;
signal present_state : TYPE_STATE;

--------------------------------- States Signals --------------------------------
signal T0_state  : STD_LOGIC;
signal T1_state  : STD_LOGIC;
signal T2_state  : STD_LOGIC;
signal T3_state  : STD_LOGIC;
signal T4_state  : STD_LOGIC;
signal T5_state  : STD_LOGIC;
signal T6_state  : STD_LOGIC;
----- Initial Signals -----
signal  S_M_1_sig       : STD_LOGIC_VECTOR(1 downto 0);
signal  S_M_2_sig       : STD_LOGIC_VECTOR(1 downto 0);
signal  S_M_3_sig       : STD_LOGIC_VECTOR(1 downto 0);
signal  Select_1_Sig    : STD_LOGIC;
signal  Select_2_sig    : STD_LOGIC;
signal  mode_1_Sig      : STD_LOGIC;
signal  Select_3_sig    : STD_LOGIC;
signal  mode_2_sig      : STD_LOGIC;

signal    L_in          : STD_LOGIC :='1';
signal    L_out         : STD_LOGIC :='1';

signal  Count_in        : integer := 0 ;
signal  Count_out       : integer := 0 ;
signal  Count_in_Flag   : STD_LOGIC ;
signal  Count_out_Flag  : STD_LOGIC ;

begin
------------------------------ sequential part of state machine -----------------
sequential : process(CLK, next_state, CLR)
begin
if(CLR = '1')then
present_state <= RESET;
elsif(CLK = '1' and CLK'event)then
present_state <= next_state;
end if;
end process sequential;

------------------------ combinational part of state machine---------------------

combinational : process(present_state, Count_in, Count_out)

begin
case present_state is
when RESET =>
next_state  <= T0;
when T0 =>
If ( Count_in /= 2) then
Count_in <= Count_in +1;
next_state <= T1;
else
L_in <='0';
Count_in_flag <= '1';
next_state <= T1;
end if;
when T1 =>
next_state <= T2;
when T2 =>
next_state <= T3  ;
when T3 =>
If ( Count_in /= 2) then
next_state <= T4;
Count_in <= Count_in +1;
else
L_in <='0';
Count_in_flag <= '1';
next_state <= T4;
end if;
when T4 =>
If ( Count_in /= 2) then
next_state <= T5;
else
L_in <='0';
Count_in_flag <= '1';
next_state <= T5;
end if;
when T5 =>
If ( Count_out /= 2) then
next_state <= T6;
else
L_out <='0';
Count_out_flag <= '1';
next_state <= T6;
end if;
when T6 =>
if ( Count_in /= 2) THEN
next_state  <= T4;
Count_in <= Count_in +1;
Count_out <= Count_out +1;
elsif (Count_out /= 2) then
next_state  <= T4;
Count_out <= Count_out +1;
else
next_state <= FINISH;
end if;
when others =>
next_state <= FINISH;
end case;
end process combinational;

Code:
WARNING:Xst:737 - Found 1-bit latch for signal <Count_in<31>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_in<30>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_in<29>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_in<28>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_in<27>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_in<26>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_in<25>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_in<23>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_in<22>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_in<21>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_in<20>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_in<19>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_in<18>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_in<17>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_in<16>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_in<15>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_in<14>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_in<13>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_in<12>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_in<11>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_in<10>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_in<9>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_in<8>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_in<7>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_in<6>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_in<5>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_in<4>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_in<3>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_in<2>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_in<1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_in<0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <L_in>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_out<31>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_out<30>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_out<29>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_out<28>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_out<27>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_out<26>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_out<25>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_out<24>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_out<23>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_out<22>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_out<21>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_out<20>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_out<19>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_in<24>>. Latches may be generated from incomplete case or if statements. We dWARNING:Xst:737 - Found 1-bit latch for signal <Count_out<18>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_out<17>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_out<16>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_out<15>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_out<14>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_out<13>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_out<12>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_out<10>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_out<9>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_out<8>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_out<7>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_out<6>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_out<5>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_out<4>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_out<3>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_out<2>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_out<1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Count_out<0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.

Regards
Mostafa

#### std_match

I know that textbooks often propose the dual-process state machine description,
but I have never met someone that can explain the advantage.
I think it s*cks. It makes the code hard to read, and for an FPGA, you don't want the state machine outputs from combinatorial logic, you want them directly from registers.

You get the warnings because you have several paths in the combinatorial process that
don't assign a value to "Count_in" and "Count_out". That is not good.

Paths without an assignment in a clocked process are acceptable, so if you think your logic is correct
I suggest that you rewrite the state machine as one clocked process.

Last edited:
sheikh

### sheikh

Points: 2

#### K-J

Hello Dears
could you please tell me how can i remove these warnings? I didn't have any idea for using latches also I have not any incomplete "Case" or "if" statement!! ( maybe i cant recognize all conditions!!)

One example...
Code:
      when RESET =>
next_state  <= T0;
There is no assignment to 'Count_In', 'L_in' or 'Count_in_flag' which are in other branches. Therefore when the 'RESET' branch is taken, those signals will not get updated. Since this is a combinatorial process, this would get implemented with a latch. I suspect that the other branches have similar missing assignments.

Combinatorial processes are a very error prone way to design. Consider (strongly) ditching them and adopting a synchronous design approach instead. Use concurrent statements for those things that can't wait one clock cycle.

Kevin Jennings

#### sheikh

Thanks dear std_match.

Use concurrent statements for those things
Thanks a lot dear Kevin, i use this one instead of the first one.
Code:
  combinational : process(present_state, Count_out_flag, Count_in_flag)

begin
case present_state is
when RESET =>
next_state  <= T0;
when T0 =>
next_state <= T1;
when T1 =>
next_state <= T2;
when T2 =>
next_state <= T3  ;
when T3 =>
next_state <= T4;
when T4 =>
next_state <= T5;
when T5 =>
next_state <= T6;
when T6 =>
if ((Count_out_flag and Count_in_flag ) = '1' ) THEN
next_state <= FINISH;
else
next_state  <= T4;
end if;
when others =>
next_state <= FINISH;
end case;
end process combinational;

Count_in        <= Count_in +1 when ( (present_state = T0) and (Count_in /= 2) ) else
Count_in +1 when ( (present_state = T3) and (Count_in /= 2) ) else
Count_in +1 when ( (present_state = T6) and (Count_in /= 2) ) else
0;

Count_out      <= Count_out +1 when ( (present_state = T6) and ( Count_in /= 2  ) ) else
Count_out +1 when ( (present_state = T6) and ( Count_out /= 2 ) ) else
0;

Count_in_flag  <= '1' when ( (present_state = T0) and ( Count_in = 2  ) ) else
'1' when ( (present_state = T3) and ( Count_in = 2  ) ) else
'1' when ( (present_state = T4) and ( Count_in = 2  ) ) else
'0';

L_in           <= '0' when ( (present_state = T0) and ( Count_in = 2  ) ) else
'0' when ( (present_state = T3) and ( Count_in = 2  ) ) else
'0' when ( (present_state = T4) and ( Count_in = 2  ) ) else
'1';

Count_out_flag <= '1' when ( (present_state = T5) and ( Count_out = 2  ) ) else
'0';

L_out           <= '0' when ( (present_state = T5) and ( Count_out = 2  ) ) else
'1';
Did mention to this?
The warnings removed. but when I try to simulate this one, the outputs of isim always stay at zero!!! without any change. and in console shows:
"ERROR: at 5 ns(10000): Iteration limit 10000 is reached. Possible zero delay oscillation detected where simulation can not advance in time because signals can not resolve to a stable value"
and mention to process and to this part of code "when T0 => next_state <= T1;". Do you know why this happen?
Regards
Mostafa

#### K-J

i use this one instead of the first one.
The warnings removed. but when I try to simulate this one, the outputs of isim always stay at zero!!! without any change. and in console shows:
"ERROR: at 5 ns(10000): Iteration limit 10000 is reached. Possible zero delay oscillation detected where simulation can not advance in time because signals can not resolve to a stable value"

The following code is a problem...Count_out will keep incrementing without a clock
Code:
 Count_out      <= Count_out +1 when ( (present_state = T6) and ( Count_in /= 2  ) ) else
Count_out +1 when ( (present_state = T6) and ( Count_out /= 2 ) ) else
Kevin Jennings

##### Full Member level 6
Actually Count_in has the same problem and is also using present_state == T0 (which by the way is written incorrectly as present_state = T0)

So when the FSM goes into T0 the simulator can never resolve Count_in as it is unstable forever.

BTW std_match, the issues the OP is having IS the primary reason you should code FSMs in the two or even three always blocks. Less room for errors like the OP is having. Well as long as you use proper syntax and put the counter in a registered always block ;-)

Regards,
-alan

Last edited:

#### std_match

BTW std_match, the issues the OP is having IS the primary reason you should code FSMs in the two or even three always blocks. Less room for errors like the OP is having. Well as long as you use proper syntax and put the counter in a registered always block ;-)
I don't get it. The original problem is unwanted latches. It is impossible to get such problems if the whole state machine is coded in one clocked process. The synthesized code will also be suitable for FPGA's, where you want all the logic before the registers, and the state machine outputs directly from registers.
The outputs will also be glitch-free.

#### K-J

the issues the OP is having IS the primary reason you should code FSMs in the two or even three always blocks. Less room for errors like the OP is having. Well as long as you use proper syntax and put the counter in a registered always block ;-)

You've got that backwards. The issues that the OP is having are typical when using any number of unclocked processes. Presumably you meant to say "the primary reason you should not code FSMs in the two or even three...".

That's not to suggest that such styles can't be made to work, it's just that using those styles is potentially more error prone, and is more typing and more work than the alternative of only using clocked processes. After that extra work and fixing those bugs that happened to not just be 'potential', the end result is not 'better' by any metric that has ever been put forth by those who choose to use it because they prefer it.

Kevin Jennings

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