hamid123
Newbie level 5
how i should design a reset pulse generator in a neural amplifier ?
i am designing a neural amplifier from a paper.it make the bits lower by lowering amplitude for optimization in a/d. i uploaded a picture that shows the general circuit .it has an ota and 2 comparator an or and reset pulse generation block . i know the internal circuit of all of the blocks unless the reset pulse generation block that i cant find out what is the internal circuit of that. can anyone help me ? the ieee link to the paper is below thanks .
https://ieeexplore.ieee.org/document/6709768/
i am designing a neural amplifier from a paper.it make the bits lower by lowering amplitude for optimization in a/d. i uploaded a picture that shows the general circuit .it has an ota and 2 comparator an or and reset pulse generation block . i know the internal circuit of all of the blocks unless the reset pulse generation block that i cant find out what is the internal circuit of that. can anyone help me ? the ieee link to the paper is below thanks .
https://ieeexplore.ieee.org/document/6709768/