fpga gate size
Most ASICs can be implemented with an FPGA. The typicall reasons why an ASIC might not be transferable to an FPGA are:
(a) the ASIC has significant analog content on the chip,
(b) the ASIC is very high performance, or
(c) the ASIC is extremely large (transistor count).
The real question is not whether it can be done as an FPGA or not, but which choice, overall, is cheaper. This can be a complex consideration, but the general principle is that FPGAs are cheaper to design, but have a higher unit cost. For example, it may cost you $0.5M to design the FPGA implementation and $4M to design the ASIC version. But the FPGA costs $20 per chip while the ASIC costs $5 per chip. So, if you are going to manufacture more than 230k chips, the ASIC is cheaper. For smaller volumes, the FPGA is cheaper. This is simplified, and other considerations also play an important role. For example, the ASIC will also take longer to design, and cannot be changed easily.
The result in the market has been that FPGA have taken over the low and mid-level ASIC designs. ASICs are usually mainly used for high-volume, high-performance chips (processors) and mixed analog/digital chips (wireless). There are even some very big FPGAs available today, but they are very expensive and the costs to design them are starting to approach the cost of designing an ASIC.
Your second question seems to relate to how the "size" of a chip is measured in gates or gate-equivalents. An FPGA has a fixed and pre-determined number of gates available on the chip, so you would think this is a good measure for size. But in fact "gates" is a very weak size metric. For example, does a flip-flop or a mux count the same as an inverter? On an ASIC it gets even harder: How many "gates" are there in a PLL or a power controller or a RAM? That is where the "gate-equivalent" metric comes in. The gate-equivalent metric attempts to normalize the "gate count" of different objects by estimating how the element compares to a number of 2-input-NANDs. For example, some marketing departments estimate a flip-flop to be equivalent to about 6 2-input-NANDs. Other companies say, no it is closer to 8 because ours have enable pins - You see this is largely a silly exercise.
I suspect that you are trying to compare the "size" of an ASIC to the advertised marketing "size" of an FPGA. These "gate count" numbers can only be very rough guides.
The true, accurate metrics are either:
(a) the number of transistors on the chip. This is a measure of how difficult it was to manufacture.
or (b) the number of placeable objects in the design (RAM= one object; FF= one object; inverter = one object). This is a measure of how hard it was to design.
Hope this helps
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