Sep 14, 2005 #1 H holddreams Full Member level 6 Joined Aug 2, 2005 Messages 351 Helped 15 Reputation 30 Reaction score 7 Trophy points 1,298 Location Shanghai Activity points 4,237 For a NMOS open-drain comparator circuit, how to reduce the “Response time High to Low”? Thanks.
Sep 15, 2005 #2 S sunking Advanced Member level 3 Joined May 25, 2004 Messages 873 Helped 70 Reputation 140 Reaction score 23 Trophy points 1,298 Activity points 6,283 enlarge the w/l of nmos
Feb 20, 2006 #3 B birdiee470 Junior Member level 3 Joined Oct 28, 2005 Messages 27 Helped 4 Reputation 8 Reaction score 0 Trophy points 1,281 Activity points 1,428 Re: How to reduce the “response time High to Low”? the more u increase w/l will make your layout area large.so think before u design, have a nice day
Re: How to reduce the “response time High to Low”? the more u increase w/l will make your layout area large.so think before u design, have a nice day
Feb 20, 2006 #4 D dwilliam Newbie level 5 Joined Feb 20, 2006 Messages 8 Helped 3 Reputation 6 Reaction score 3 Trophy points 1,283 Activity points 1,356 If the issue is fall-time, then you may consider using a number of well dimention inverters before the last MOS
If the issue is fall-time, then you may consider using a number of well dimention inverters before the last MOS