How to reduce route delay???

[hfly47]

Hi,

I just met a setup violation in which the route delay took more than 90% of the total data path delay? How to reduce it?

PS: The device I used is Virtex-5.

 

[asjohnas]

You need to use constraints and try to increase number of pipe-line registers.
You can try to see your problem in FPGA editor or PlanAhead and it will give your idea.

 

[hfly47]

You need to use constraints and try to increase number of pipe-line registers.
You can try to see your problem in FPGA editor or PlanAhead and it will give your idea.

I couldn't change the pipeline registers since this is a ASIC prototyping.
Are there other soluations suggetsted?
Thanks~

 

[sameh_yassin99]

Hi,
This problem is not a peace of cake. I'm saying that because theoritical solutions are too many, but applying them is not that easy. I tried it myself but I'm still suffering from this problem. However, I'll share with you some of the solutions.
1- Take care of the clocking infra structure. Use clock global buffers for long routes.
2- Avoid incomplete if statements
3- Remove the synthesis warnings as you can
4- The most important, is to partition your design using floorplanning.

if you need any more details about the above solutions, please reply to me because, as I said before, still suffering from your problem !

Best wishes,
Sameh yassin

 

[bapodradhairyab]

have you tried using constraints in ucf files... this was worked for me...

 

[hfly47]

have you tried using constraints in ucf files... this was worked for me...

Hi, bapodradhairyab
Could you tell me what constraints could work?
Thanks a lot

 

[bapodradhairyab]

which ever signals are following critical path or for the signals you are facing trouble you can use timing constraint. i don't remember exactly how to use it but, you can assign delays like combinational logic should reach to reg input in particular amount of time... sort of constraints are there... you have to find out syntax as i dont remember it...