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How to reduce Over-shoot and Under-shoot Problems?

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Apr 22, 2011
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Over-shoot and Under-shoot effect mostly occur in digital gates, sometimes it may affect the noise margin of the gate and even damage the internal FET of the gate IC. My question is How to reduce or avoid this Over and Under shoots effects in Digital Gate ICs?

Overshoots appear unavoidable when sending rapid current changes through IC's.

Spec sheets often have a graph showing an output pulse with overshoot/undershoot.

IC operating requirements state that a capacitor across supply pins will reduce spiky transitions.

FET inputs have certain restrictions lest they fry.

Thanks for your Replays,


Overshoots are unavoidable, its OK. But we can reduce it, right? How do it!


I am not saying with the transmission line, i am discuss with the shooting effects in the output of a digital IC. OK, leave it. If we match it with a characteristics impedance, then we can avoid the shooting effect. How to match it in a Gate IC? Can you give us any example?
I think, we may introduce some series resistance to reduce the shoot problems. But it may affect the slew rate of the signal!

Is it correct? Since slew rate depends on the frequency of the signal, but resistance could not affect the frequency in anyway!

There are basically two kinds of transmission line impedance matching, source side (series termination) and load side (parallel termination). As you can easily see, source series termination is preferable, because it doesn't introduce additional power dissipation.

My question is How to reduce or avoid this Over and Under shoots effects in Digital Gate ICs?
The question isn't quite clear. Without transmission lines of some length between gates, no overshoot will occur.

Digital ICs are however often ultilizing the output driver impedance (by adjusting the transistor areas) for impedance matching. You have e.g. programmable drive strength respectively output series termination (another word for the same thing) in FPGA and recent CPLD. But artificial output impedance increases the logic delay and rise/fall time with capacitive loads, so it's not wanted in every case. It's not reasonable to provide 50 to 80 ohm impedance required to match usual single ended PCB traces with logic ICs for general purpose, because they'll be to slow with capacitive load. If programmable drive strength isn't an option, external series termination should be considered.

The question isn't quite clear. Without transmission lines of some length between gates, no overshoot will occur. you told overshoot and undershoot problems occur in Gate ICs due to transmission lines. But while i was worked in most of gate ICs, there is a same effect exist in the output of Gate IC even no wires connected from that Gate. i am getting a thinking mood on " what is the source of overshoot and undershoot?" From where it exist? Because this effect increases with increase in frequency range!

I think you should be more clear about the hardware setup of interest. The question has been posted in the "Analog Circuit Design" forum. So I won't expect a GHz IC design problem in the first place. Of course, interconnect lines inside an IC have to be treated as transmission lines above a certain frequency, e.g. for length > λ/20 .. λ/10.

If you are referring to external wiring of ICs on PCBs, yes overshoot may occur. Mainly if you don't consider the transmission line nature of interconnect traces and circuit inductances.

Finally, to mention a trivial fact. You'll get usually overshoots in your oscilloscope waveform with inappropriate signal probing. That's not primarly a circuit design problem, however.

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