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In my past experience, this kind of warning from so called HDL assistant tool means nothing, so I never take them into considerations. And I also suggest not try to fix this kind of warning in the synthesis step, it will result in a larger design. Modern layout tools are able to deal with them very well.
As a compromise between all suggestions to solve the problem, you can try the solutions of using attributes or buffer insertion then simulat your design and check the violation that my appear and enhance your design according to the results you get.