How to reduce EMI in analog IC pad design

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michaeljackson

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Hi all,

I designed some I/O and passed ESD test. But customer asks me to lower rise/fall time of voltage output for reducing EMI. I donot know how to do with it . Firstly I think I can segment output driver of IO pad, but it seems it is not very useful.

Can anybody show me how to do with pad design? Thank you very much. Or show me some paper, then I can refer it.
 

You just need a weaker drive, ie lower W/L in output stage.
Of course, the challenge is in dealing with the additional delay caused by longer rise/fall times.
 

Series gate resistance or an undersized predriver will give
you a slew-rate-limited driver (Miller capacitance*dV/dt
vs available gate drive). Controlling slew rate internally
is better than using a weak driver and counting on load
capacitance to limit voltage edge rate, less board level
loading variability in timing.

You can also segment and time-cascade the outputs if
you have enough edge time allotted. Have seen LVDS
drivers done this way. Be sure you segment them odd
rather than even, or you'll get a "porch" right at the
threshold when you'd rather step across it smartly.
 
Thank you, Dick and checkmate, I will try your ideas.
 

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