4608 is the number of logic elements of your device. It also has a lot of RAM...
My first guess - you use a lot of D Flip Flops and little RAM.
Questions:
1. What makes you think that your code is ought to fit in that device in the first place? Is it an existing design ?
2. From the Quartus synthesis report - how many D Flip Flops does your design consume ?
3. Does your design make use of division operations ?
4. What entity consumes the most amount of logic? What does it do ?
The reported error doesn't imply that they have a problem with the number of flip-flops in the design.
The OP needs to post their code as TrickyDicky suggests, I suspect the code is probably not optimally done for an FPGA design and has excessively large combinational logic.