How to reduce combinational node in FPGA design?

[hoheiho]

Hi all,

I am using a low cost FPGA (EP2C5T144C6) and trying to compile my verilog code in Quartus II.

The error message come out:
Error (170011): Design contains 5204 blocks of type combinational node. However, device contains only 4608.

I have try to reduce some If,Else case but it has no big different. Is there any suggestions that i can try to solve this problem??

Thanks

 

[TrickyDicky]

Use a bigger device?

 

[FvM]

You'll analyze thoroughly where the design resources go. In some cases, parallel can be replaced by sequential logic.

 

[shaiko]

Is it possible that you didn't clean your code and it has many latches instead of DFF ?

 

[hoheiho]

Thanks for the reply

Use a bigger device?

I cannot use a bigger device since thats the only FPGA I got and also the PCB connection

You'll analyze thoroughly where the design resources go. In some cases, parallel can be replaced by sequential logic.

Sorry, I know wt means by sequential logic but wt is the meaning of parallel?

Is it possible that you didn't clean your code and it has many latches instead of DFF ?

I am using only a few latch and most of them are DFF

 

[TrickyDicky]

The fact that you are using any latches usually points to poor design practice. WHy not post the code thats causing the problem?

 

[shaiko]

Your FPGA:
https://www.digikey.co.il/product-detail/en/EP2C5T144C6/544-2136-ND/1468677

4608 is the number of logic elements of your device. It also has a lot of RAM...
My first guess - you use a lot of D Flip Flops and little RAM.

Questions:

1. What makes you think that your code is ought to fit in that device in the first place? Is it an existing design ?
2. From the Quartus synthesis report - how many D Flip Flops does your design consume ?
3. Does your design make use of division operations ?
4. What entity consumes the most amount of logic? What does it do ?

 

[ads-ee]

4608 is the number of logic elements of your device. It also has a lot of RAM...
My first guess - you use a lot of D Flip Flops and little RAM.

All we can determine from the OP's original post is that they are using too many LUTs.

Error (170011): Design contains 5204 blocks of type combinational node. However, device contains only 4608.

The reported error doesn't imply that they have a problem with the number of flip-flops in the design.

The OP needs to post their code as TrickyDicky suggests, I suspect the code is probably not optimally done for an FPGA design and has excessively large combinational logic.

Regards