How to reduce clock speed in Spartan 2e FPGA?

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usman

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Assalam o Alaikum to All!!!
i faced a simple problem while working on FPGA>>>i am using spartan2e FPGA & D2SB board, as u might know the clock speed of this FPGA is 50Mhz. i wanted to run a simple sequential component(JK FFP) on it, all the combinations of J&K input of JK Flip Flop works fine but when both input becomes 1 then output is not valid cause of high speed i don't see togling........so what should be done to see a clear togling on the output. in other words how to reduce the clock speed and use in my design....
regards,
Muhammad Usman
 

Re: reducing clock speed

you can very well type a module which counts the clock positive edge and producing your own clock signal.
 

reducing clock speed

usman, I don't understand "output is not valid". The flop should be outputting a 25 MHz square wave, clearly visible on almost any oscilloscope. What do you see instead?
 

reducing clock speed

Hi,
hope u r trying to watch the output of the FlipFlops on the LEDs. ur eyes can't work that fast. try to c that in a scope or try to reduce the speed of ur Clk, so that u can see the toggling on the Leds itself. Use a 26 bit counter and give it's MSB bit to clock ur J&K. The u should be able to see the LEDs toggling at 1sec.
 

Re: reducing clock speed

Dear echo!!
i mean from my statement"output is not valid", is that i can't see my output toggling, rather the output is dim on....as i am using LED for the output. i know that the frequency is much higher so i can't see clearly,,,but i want to know how to reduce the speed of blinking so that i see the output(LED) togling very clearly,,,,,
i am toggling the output on positive edge of clock in my code for FFP.

kind regards,
Muhammad Usman
 

reducing clock speed

Ok, an LED at 25 MHz would be a problem.

Here is a small Verilog module that divides the 50 MHz clock by 2^24 to generate a 3 Hz enable signal, and then uses it to toggle a flop. This is fully synchronous.

Code: 
module top (clk, out);
  `define CBITS 24                  // 50 MHz divided by 2^24 gives about 3 Hz
  input                 clk;
  reg      [`CBITS-1:0] cnt=0;      // counter
  reg                   slow=0;     // slow pulses
  output reg            out=0;

  always @ (posedge clk) begin
    cnt <= cnt + 1;
    slow <= (cnt == 0);             // one pulse per cnt cycle
    if (slow) begin
      out <= ~out;                  // toggle the output
    end
  end
endmodule

Here's a non-synchronous method. It generates a new buffered slow clock:

Code: 
module top (clk, out);
  `define CBITS 24                  // 50 MHz divided by 2^24 gives about 3 Hz
  input                 clk;        // fast input clock
  reg      [`CBITS-1:0] cnt=0;      // fast clock divider
  wire                  slowclk;    // slow clock
  output reg            out=0;

  always @ (posedge clk) begin      // generate the slow clock
    cnt <= cnt + 1;
  end

  BUFG buf1 (.I(cnt[`CBITS-1]), .O(slowclk)); // buffer the slow clock

  always @ (posedge slowclk) begin
    out <= ~out;                    // toggle the output
  end
endmodule

I tried those with Spartan-3 using ISE 8.1.01i. I don't have Spartan-IIE stuff installed.
 

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