How to recognize the DFF in the phase detector ?

[JobsEDA]

dear all

the books said the phase detector is composed with two dff and an and gate.

but I wonder how to view this circuit as DFF

could you help me to understand it ?

Thanks

 

[leo_o2]

Please be aware of that some phase detector don't use DFF.

 

[JobsEDA]

Please be aware of that some phase detector don't use DFF.

Dear Leo

You mean this PD don't use DFF and just only two latch ?

Thanks

 

[leo_o2]

Please search pre-charge type PFD. No dff is needed.

---------- Post added at 12:43 ---------- Previous post was at 12:34 ----------

http://steps-india.com/ijaea/IJAEA-Jan-2011-II-21.pdf

 

[erikl]

the books said the phase detector is composed with two dff and an and gate.
but I wonder how to view this circuit as DFF

The 2 NOR-latches are equivalent to DFFs whose D (data) inputs are fixed to VDD -- as indicated in your figure above. And these "minimized" DFFs also don't own SET & RESET inputs.

 

[JobsEDA]

The 2 NOR-latches are equivalent to DFFs whose D (data) inputs are fixed to VDD -- as indicated in your figure above. And these "minimized" DFFs also don't own SET & RESET inputs.

Thanks for your explanation.
But I still can't figure out.
Could you give the original DFF before it is minimized and remove its D input ?
Thank you very much

 

[leo_o2]

erikl means "equivalent" not same.
In fact, DFF is much complex.

 

[FvM]

Most DFFs are essentially comprised of cascaded (master-slave) latches. The first stage latches the input during clock low state, the second the output of the first stage during clock high. So effectively, the input state is sampled on the rising edge of clock. The implementation can be different, either using logical gates only (bipolar), or a combination of logical gates and transfer switches in CMOS technology, see below.