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Please be aware of that some phase detector don't use DFF.
the books said the phase detector is composed with two dff and an and gate.
but I wonder how to view this circuit as DFF
The 2 NOR-latches are equivalent to DFFs whose D (data) inputs are fixed to VDD -- as indicated in your figure above. And these "minimized" DFFs also don't own SET & RESET inputs.