The 2 NOR-latches are equivalent to DFFs whose D (data) inputs are fixed to VDD -- as indicated in your figure above. And these "minimized" DFFs also don't own SET & RESET inputs.
The 2 NOR-latches are equivalent to DFFs whose D (data) inputs are fixed to VDD -- as indicated in your figure above. And these "minimized" DFFs also don't own SET & RESET inputs.
Thanks for your explanation.
But I still can't figure out.
Could you give the original DFF before it is minimized and remove its D input ?
Thank you very much
Most DFFs are essentially comprised of cascaded (master-slave) latches. The first stage latches the input during clock low state, the second the output of the first stage during clock high. So effectively, the input state is sampled on the rising edge of clock. The implementation can be different, either using logical gates only (bipolar), or a combination of logical gates and transfer switches in CMOS technology, see below.