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The read-modify-write is typically a processor-style instruction which still requires multiple memory accesses and doesn't necessarily require a dual-port memory. The key element is that the instruction is protected from interrupts so that the read-modify-write is guaranteed to execute without interruption from another process.
With a dual-port memory, you would need to implement this protection in hardware via a memory controller that would guarantee that once a RMW cycle started on the first port, no access to the second port would be allowed to the same address until the write has occurred -- or vice-versa. This is not a simple hardware circuit so typically dual-port memory multi-access protection schemes are implemented in software with mutexes or semaphores to control access to shared memory areas.
By "single-cycle" I assume you mean a single processor instruction? Because, this cannot happen in a single memory cycle. You would need at least two memory cycles, one to read and the second to write back modified memory contents -- no matter how many ports the memory has.
"A synchronous RAM cannot perform read-modify-write operations in a single clock
cycle, but the dual-port, synchronous block RAM in all Xilinx® FPGAs can pipeline
the write operation and achieve a throughput of one read-modify-write operation per
clock cycle. To do so, the designer uses Port A as the read port, uses Port B as the write
port, and uses one common clock for both ports. The read address is routed to Port A.
A copy of the read address is delayed by one clock and routed to Port B. The data from
Port A is modified and used as the data input to Port B"