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How to realize a Read- modify -write in single cycle using a Dual Port RAM

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blooz

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How to realize a Read- modify -write in single cycle using a Dual Port RAM?
 

grieblm

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The read-modify-write is typically a processor-style instruction which still requires multiple memory accesses and doesn't necessarily require a dual-port memory. The key element is that the instruction is protected from interrupts so that the read-modify-write is guaranteed to execute without interruption from another process.

With a dual-port memory, you would need to implement this protection in hardware via a memory controller that would guarantee that once a RMW cycle started on the first port, no access to the second port would be allowed to the same address until the write has occurred -- or vice-versa. This is not a simple hardware circuit so typically dual-port memory multi-access protection schemes are implemented in software with mutexes or semaphores to control access to shared memory areas.

By "single-cycle" I assume you mean a single processor instruction? Because, this cannot happen in a single memory cycle. You would need at least two memory cycles, one to read and the second to write back modified memory contents -- no matter how many ports the memory has.
 
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j_andr

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if your clock is not too fast you can try the example I gave in the thread:
Continuous sampling 3GSPS ADC and Altera FPGA interface
---
J.A
 
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blooz

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I found this from a Xilinx White paper

"A synchronous RAM cannot perform read-modify-write operations in a single clock
cycle, but the dual-port, synchronous block RAM in all Xilinx® FPGAs can pipeline
the write operation and achieve a throughput of one read-modify-write operation per
clock cycle. To do so, the designer uses Port A as the read port, uses Port B as the write
port, and uses one common clock for both ports. The read address is routed to Port A.
A copy of the read address is delayed by one clock and routed to Port B. The data from
Port A is modified and used as the data input to Port B"
...
 

grieblm

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If the read address is delayed by one clock than how does this work in one clock cycle. It still sounds like two to me. Of course, the 2nd write cycle is hidden so I guess it can be ignored. ;-)
 

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