I don't understabd some of the contributions. If we're talking of FPGA with RAM based configuration and external configuration memory, the configuration can be read out from the memory in most cases and always captured at the configuration interface. Configuration readout from the FPGA isn't provided with most FPGA (except e.g. Xilinx Virtex devices) to simplify the hardware rather than for security reasons.
Some FPGA families, e.g. some Altera Stratix and Xilinx Virtex have a bitstream encryption option, in this case the configuration bitstream is worthless without knowing the key stored inside the FPGA.