How to read register of size 32 bit using I2C?

[sriharsha.hs]

Hello folks,

I am communicating bw FPGA and a processor using I2C, where processor is a I2C master and FPGA is a slave.

I need to assign all the register width to 32 bit using 8 bit register address.

How to read/write data from register of size 32 bit wide.? I am using I2C slave which can be read and written, each reg having 8 bit wide and pointed by 8 bit wide address.?

What changes have to be done in my slave side?

Please hep guys

 

[andre_luis]

The master device ( FPGA ) must manage byte allocation by a simple ring counter modulo-4 ( 0 to 3 ), on reading and writing process. Nothing to do on slave side.


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[sriharsha.hs]

Hi andre_teprom,

Well, thanks for replying back. I just wanted to clarify that, the master device you mentioned is FPGA. But I in my context it is some external processor which is I2C master. I would also like to ask you that, how can master device will read 32 bit data continuously or in four transaction as it only sends 8 bit register address at once. Because, once the master receives 8 bit of data from slave, it acknowledges to slave that it has received. How does my I2C slave get to know to send next set of 8 bit data and so on..?

As per the protocol standard, for every 8 bit of transaction, either the master or the slave expects for an acknowledgement. I am pretty much confused about handling at the slave part?

Please, elaborate on this.

Thank you.

 

[andre_luis]

Storage devices 24xx have 2 communication modes built in I2C protocol: single byte ou Block.
Decision about which to choose depends on data amount, but I suggest you start with the simplest one.

For addressing each data on 24xx device you must access individually each byte.
Just to check: The external processor you mentioned, work with C language ? What processor ?


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[FvM]

The I2C spec describes multi byte transmissions. A 32 bit read can be simply understood as a sequence of 4 byte reads. All details are up to you, e.g. the byte order or what happens after 4 bytes have been read. For addressable data entities, it's a usual option to proceed automatically with the next address.

 

[sriharsha.hs]

Hey FvM,

Thanks for writing on this thread. regarding the multibyte transaction, I just wanted to know, whether reading sequence of 4 bytes will be followed continuously register address + offset or using Repeated read bit transcation.
The spec i2c spec (NXP) says about multibyte transmission and says about multibyte read and write. PLease describe much in detail about.
I have attached the snapshots of the i2c spec manual.
Thank you.

 

[FvM]

reading sequence of 4 bytes will be followed continuously register address + offset or using Repeated read bit transcation.

You are asking exactly what?

If you add 2 more byte reads to figure 12, you get a basic 32 bit read.

The example expects that no register address is required to access the slave data, otherwise the transactions becomes more complex.