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try to use amplify from synplicity ot presission synthesys from mentor to optimise your rtl design.
you can also use flor planer in manual mode to reduce the critical paths.
it is more of guss work but can give you good results.
hock
You should have a timing closure methodology, mostly it will depend on "how much did u miss your clock"
after anything you should use a good coding style methodology "stick with reuse methodology manual book" unless your design have unavoidable asynchronous events.
In general you can meet your time according to result clock speed to required clock speed ratio:
some times it can be solved with applying more effort on PAR, "take care the PAR results always are 10% less than whatyou will get on hardware", this 10% can be done with higher effort on PAR, multi-pass par.
if you missed with 20% to 75% u may apply critical path timing constraints, static timing analysis for the design "critical paths", check your modular design in PAR, apply placement constraints "floorplanning", rgister duplication for large fanout,synthesis tool effort and global timing constraint ,consider some pipelining.
if you missed it with so much, i.e. you want a 100 MHz and you get 30 more than 100%, then I believe you should check your hierarchial design, coding style, synthesis tool constraints, consider pipelining for the whole design modules, change the whole design.
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