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How to prototype a multi-processor based SoC (ASIC)?

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LucienZ

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Dear all, I want to ask you questions regarding multi-processor SoC prototyping and verification. I see many SoC chips come with more than one processor cores, e.g. the OMAP3530 contains a Cortex-A8 and a TMS320DM64+ (and many other peripherals). I want to know how does TI make a prototype for such a design? Do they even use FPGAs before an ASIC layout?

Well the above example perhaps looks too comlplex. Now if I want to design a dual processor SoC with three or four customized periphrals, the first idea I can get is to use a FPGA chip for prototyping my design. But now the problem is: what processors I should choose for my SoC and how to verify the whole system's functionality?

There are many soft cores designed for FPGA implementations, such as MicroBlaze, Nios and Cortex-M1. But I think their architectures and instruction sets are not very compatible with ASIC processor IPs. Now if I want to finalize a SoC (ASIC implementation) with two Cortex-A8 processors, how can I prototype my design with self-designed peripherals and on-chip interconnections? I guess that using MicroBlaze or Cortex-M1 is not a good idea, but will it be better to use Cortex-A8 test chips or so-called Soft Macrocell Models?

I hope someone can share experiences on this issue...
Thanks very much for your attention!
Lucien
 

farhada

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I sent you a private mail, if you are interested, we can discuss it off-line.

cheers,
/Farhad
 
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AdvaRes

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Dear all, I want to ask you questions regarding multi-processor SoC prototyping and verification. I see many SoC chips come with more than one processor cores, e.g. the OMAP3530 contains a Cortex-A8 and a TMS320DM64+ (and many other peripherals). I want to know how does TI make a prototype for such a design? Do they even use FPGAs before an ASIC layout?

Big companies like TI design their SoCs based on ready Verifyed IPs. Actually they have the necessary resources in term of knowledge, tools,machines to prototype directly an asic.


Well the above example perhaps looks too comlplex. Now if I want to design a dual processor SoC with three or four customized periphrals, the first idea I can get is to use a FPGA chip for prototyping my design. But now the problem is: what processors I should choose for my SoC and how to verify the whole system's functionality?

This depend on your application performance requirement. Could you please give more details ?
Its important to know that a SoC requires a considerable number of skilled guys (engineers+Phd etc..) and a lot of efforts as well as time to be designed and fabricated.

There are many soft cores designed for FPGA implementations, such as MicroBlaze, Nios and Cortex-M1. But I think their architectures and instruction sets are not very compatible with ASIC processor IPs. Now if I want to finalize a SoC (ASIC implementation) with two Cortex-A8 processors, how can I prototype my design with self-designed peripherals and on-chip interconnections? I guess that using MicroBlaze or Cortex-M1 is not a good idea, but will it be better to use Cortex-A8 test chips or so-called Soft Macrocell Models?

Network on chip can solve your problem. Actually it had been designed for this purpuse. Your SoC will integrate a NoC+heterogenous IPs+ Interfaces/wrapper to overcome the problem of IPs protocols as well as instruction sets uncompatibility.
 
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LucienZ

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Thank you farhada and AdvaRes for the responses. The target algorithm is associated with stereo matching i.e. placing two cameras like the two human eyes, estimate the depth information from the image pair, and then interpolate a plausible view like taken from an intermediate position...During the depth estimation, there are many for-loops with few data dependencies in each iteration. So I think it has the potential to be highly parallelized. The algorithm has already been implemented on PC but now can process only one such a pair in one second (Pentium IV 3.0GHz). GPU is much better, but we have some plans to go embedded and ASIC.

I will first evaluate some promising platforms and do prototyping. To achieve the best real-time performance, implement the algorithm directly using FPGA fabrics seems to be the only solution. However the MPSoC solution also came into my mind, and some of our professors and PhDs are pioneers in this field (also on the NoC architectures). After the prototyping, perhaps they also want to make an ASIC or say ASSP implementation.

I am a quite new member with the related topics. So I would like to learn knowledge on this, from both the academic and industry. AdvaRes, do you know some successful SoC products (ASIC) that employs NoC as interconnections?
 

AdvaRes

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LucienZ said:
Thank you farhada and AdvaRes for the responses. The target algorithm is associated with stereo matching i.e. placing two cameras like the two human eyes, estimate the depth information from the image pair, and then interpolate a plausible view like taken from an intermediate position...During the depth estimation, there are many for-loops with few data dependencies in each iteration. So I think it has the potential to be highly parallelized. The algorithm has already been implemented on PC but now can process only one such a pair in one second (Pentium IV 3.0GHz). GPU is much better, but we have some plans to go embedded and ASIC.

I will first evaluate some promising platforms and do prototyping. To achieve the best real-time performance, implement the algorithm directly using FPGA fabrics seems to be the only solution. However the MPSoC solution also came into my mind, and some of our professors and PhDs are pioneers in this field (also on the NoC architectures). After the prototyping, perhaps they also want to make an ASIC or say ASSP implementation.

I am a quite new member with the related topics. So I would like to learn knowledge on this, from both the academic and industry. AdvaRes, do you know some successful SoC products (ASIC) that employs NoC as interconnections?

Some companies started to use the Arteris solution in their SoC like TI, ST etc....
https://www.arteris.com/releases.htm
 

shitansh

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