Typically, If we use CPLD/EPLD, we can check the encrypt bit in the development software,
but FPGA itself cannot be protected because of the SRAM architecture.
I have one method to protect FPGA design: you can design a PRBS generator in FPGA and CPLD, the CPLD acts as the microprossor to config the FPGA, and as the decrypt seed when the FPGA configuration is complete.
in FPGA, if the seed is not equal to the PRBS generated in FPGA, the FPGA will stay in the reset state. so that we can protect our design based on FPGA.