How to protect the bitstream in Xilinx/Altera FPGA?

[clifftsai]

Hi,

Actel have some Fuse and Flash base FPGA that can protect the bitstream inf FPGA device .
Does Xilinx or Altera have similiar function or devices?

 

[tlp71@hotmail.com]

VirtexII have the feature to encrypt the bitstream with a triple des algoritm. to use this feature you need to have a backup battery to preserve your keys in FPGA device when VCC shotdown.
Bye

 

[wasp]

Try that link...

http://www.free-ip.com/copyprotection.html

 

[MegaVolt]

Other Xilinx device not have the feature to encrypt the bitstream

 

[arena_yang]

Typically, If we use CPLD/EPLD, we can check the encrypt bit in the development software,

but FPGA itself cannot be protected because of the SRAM architecture.

I have one method to protect FPGA design: you can design a PRBS generator in FPGA and CPLD, the CPLD acts as the microprossor to config the FPGA, and as the decrypt seed when the FPGA configuration is complete.

in FPGA, if the seed is not equal to the PRBS generated in FPGA, the FPGA will stay in the reset state. so that we can protect our design based on FPGA.

 

[my_garden]

I agree Arena_yang.
You can use one CPLD to encrypt the source in FPGA. You can design one key in CPLD, or put one part of logic in CPLD.

 

[tlp71@hotmail.com]

if you use a cpld to make a cypher decoder you have everithing a net where the bitstream is readable.
If you would protect VII, antifuse FPGA or Asic.

 

[allegro]

I heard that somebody can read back the decrypte CPLD.So it seemed that there is no way to protect our design.

 

[zape]

A possible solution, only valid if you produce a low number of units, is based on the use of DS2401 (a Silicon Serial Number from Dallas). Your FPGA shall read this device and check for a valid number (so you will need one configuration bitstream per FPGA).

A Xilinx application note is attached.

 

[YUV]

Wiring protection

Encryption... Decryption...
All kinds of protection need extra hardware.
:idea: I have a simpler decision, which doesn't need any hardware. You already got it! It's your PCB. You should put some connections onto internal layer. Your design can use only 2 pins (in & out) for testing PCB wiring. If wrong, :x .
I agree, simple PCB can't protect efficiently. But do you really need protection for simple project :?:
For complex design you will use multilayer PCB and (may be) FPGA in BGA package. Wiring protection will be superior :!:

PCB IS A KEY FEATURE OF DESIGN

 

[dainis]

A possible solution, only valid if you produce a low number of units, is based on the use of DS2401 (a Silicon Serial Number from Dallas). Your FPGA shall read this device and check for a valid number (so you will need one configuration bitstream per FPGA).

A Xilinx application note is attached.

Direct link:
**broken link removed**

 

[Regnum]

Encrypting the FPGA bitstream externally is useless... anyways you may sample it at the FPGA configuration pins.
Put a tiny but vital piece of code into a cheap CPLD working interlocked to the main FPGA.

 

[alixedi]

Xilinx have bit released the standard for its bitstreams ie. the bitsream cannot be reversed to get any idea of the logic implemented. However, this does not protect against mindless reverse engineering by uploading the bitstream from the configuration PROM and employing reverse engineering to duplicate the remaining PCB. To tackle this problem, you need extra hardware namely an encryption logic of some sorts to protect your design.