How to properly set chip edge in Assura DRC?

[cetianwang]

Hi,
I am doing layout in ibm cms9flp.
When running assura DRC, then I got errors like:
GR999a:All PC polygons must be within CHIPEDGE
GR999a:All M1 polygons must be within CHIPEDGE
GR999a:All (CA or CA_bar) polygons must be within CHIPEDGE
etc.
Could anyone please suggest me what can I do to satisfy this rule?

Thank you,

 

[jgk2004]

Re: how to set chipedge?

If you are going to tap this chip out, you will need a sealring, which would meet the errors your having at the chip edge. A seal ring has alot of DRC rules within it and are usually provided for you by the fab house for standard mini ASIC run(say 1mmX1mm like with euro-practice). If it is not provided it will be in your DRC/Layout guide which will be in your pdk docs, thus you need to make it yourself. If you are not going to really tap out the chip and it is just for a project these DRC errors can be ignored.

Hope this helps

Jgk

 

[cetianwang]

Re: how to set chipedge?

Thank you very much!