How to produce a synthesizable delay

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superhet

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i have a problem where data from one module has to be given to another module but with a delay. in simulation with modelsim delays can be easily generated by #<amount of delay> but how can i produce a synthesizable delay. lets say i want an equivalent of

#30

the time is in nanoseconds and the choice of the clock frequency is up to you
 

Re: synthesizable delay

the only way to produce delays in plds is to build internal timer counts according to system clock.

u simulate ur designs for functionality not for timing.

u use timing reports to see only if ur design has the appropriate speed.
 

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    superhet

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synthesizable delay

You can use synplify_pro to add route delay.
use its SCOPE
 

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    superhet

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Re: synthesizable delay

In general delay is not synthesizable unless there is a counter (similar to stopwatch) .. the delay is affected by 2 main factors :
1- gate delay ..
2- routing delay ..
if u managed ( theoritically ) to know exactly the gates that u r going to use and their delays , then the routing delay between them , then u will be able to have an accurate synthesizable delay ..
 

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