Hi ads-ee
Thank you very much for your reply. The simulator is ncverilog.
Here is my simulation results. "i" is actually 15 instead of 16 (I was using i=n-1 in my code). As you can see, at time 10, the result is x.
Yes, there have a simple way to do the comparator as you suggested ( tag_equal=!(stag^ptag)
. I am just curious why there has x in the output in the current code.
One more question is "is "disable sweep;" synthesizerble?
Thank you very much,
Brian
ncsim> run
0 stag=xxxx,ptag=xxxx,tag_equal=x, i=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
i=00000000000000000000000000001111
i=00000000000000000000000000001110
i=00000000000000000000000000001101
i=00000000000000000000000000001100
i=00000000000000000000000000001011
i=00000000000000000000000000001010
i=00000000000000000000000000001001
i=00000000000000000000000000001000
i=00000000000000000000000000000111
i=00000000000000000000000000000110
i=00000000000000000000000000000101
i=00000000000000000000000000000100
i=00000000000000000000000000000011
i=00000000000000000000000000000010
i=00000000000000000000000000000001
i=00000000000000000000000000000000
10 stag=000a,ptag=000b,tag_equal=x, i=11111111111111111111111111111111
i=00000000000000000000000000001111
i=00000000000000000000000000001110
i=00000000000000000000000000001101
i=00000000000000000000000000001100
i=00000000000000000000000000001011
i=00000000000000000000000000001010
i=00000000000000000000000000001001
i=00000000000000000000000000001000
i=00000000000000000000000000000111
i=00000000000000000000000000000110
i=00000000000000000000000000000101
i=00000000000000000000000000000100
i=00000000000000000000000000000011
i=00000000000000000000000000000010
i=00000000000000000000000000000001
i=00000000000000000000000000000000
20 stag=000b,ptag=000b,tag_equal=1, i=11111111111111111111111111111111
ncsim: *W,RNQUIE: Simulation is complete.
You might be getting z because stag and ptag don't have a stag[16] and a ptag[16] bit as they are both defined as [n-1:0] and you defined n as 16. As your for loop uses i=n;i>=0;i=i++ as the start;end;increment values the first i is 16 and it doesn't exist. Not sure why it wouldn't affect the case where the values match though.
Still not sure why you would even write code like this it is probably the worst code I've seen for doing a compare in Verilog.
Verilog compare that most coders would use.
Code Verilog - [expand] |
1
2
3
| assign tag_equal = (stag == ptag);
// or you could use this (but I prefer the previous less code to type)
assign tag_equal = (stag == ptag) ? 1'b1 : 1'b0; |
this will works regardless of the value of n you use.
- - - Updated - - -
Update:
I was curious about the Z's you claim occur in the simulation of your code. I just ran your code from post #1 in modelsim and there are no Z's anywhere in the simulation, there are X's at the beginning of the simulation for ten time steps before anything is applied to the A and B inputs.