How to print '-4', not '11111111111100'

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ruwan2

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Hi,

I read a Verilog tutorial on numeric expression. The example is:


Code Verilog - [expand]
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integer intA;
reg [15:0] regA;
 
always @ * begin
intA = -4'd12;
$display ("\$display: A0 = %b, A0 = %d", intA, intA); // 
 
regA = intA / 3;
$display ("\$display: A1 = %b, A1 = %d", regA, regA); //



The result is:

# $display: A1 = 1111111111111100, A1 = 65532


A1 is -4, but the print is '1111111111111100', or '65532'. It is different from the picture shows.



I find the following but not sign control here.



Code Verilog - [expand]
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$display("<format>", exp1, exp2, ...);  // formatted write to display
  format indication %b %B binary
                    %c %C character (low 8 bits)
                    %d %D decimal  %0d for minimum width field
                    %e %E E format floating point %15.7E
                    %f %F F format floating point %9.7F
                    %g %G G general format floating point
                    %h %H hexadecimal
                    %l %L library binding information
                    %m %M hierarchical name, no expression
                    %o %O octal
                    %s %S string, 8 bits per character, 2´h00 does not print
                    %t %T simulation time, expression is  $time
                    %u %U unformatted two value data  0 and 1 
                    %v %V net signal strength
                    %z %Z unformatted four value data  0, 1, x, z



It should be able to print '-4' as the picture show. Could you tell me that? Thanks,
 

%b prints binary, %d prints in decimal format. And you want to use reg signed there. In the same way you use "wire signed".
 
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    ruwan2

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hai
check this document
**broken link removed**

it will help you
 

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