How to prevent a module from synthesis in FPGA flow

[tariq786]

Hi guys,

Hope you are good.I have couple of modules in a hierarchy. That is





TopModule

-----> module 1

-----> module 2

-----> module 3







I want to synthesize all modules including TopModule except module3. How to prevent module3 from synthesizing, translating, mapping and P&R.





Any ideas!!!





Thanks

 

[zula]

You should not instantiate module 3 in your topmodule.

 

[tariq786]

Hey Zula,
Then how is the overall system going to work?

 

[kvingle]

are you using xilinx or altera...?
If you are using Xilinx then refer to incremental synthesis feature ...
refer to dev guide or **broken link removed**

 

[Maxwell077]

Hi,
Your problem isn't clear. You don't want to be synthesized your module and you want whole system is goin' to work properly. If module 3 isn't going to be there, how can it affect your system..

Do you want to use module 3 or not? If you don't want this module in your design, you won't instantiate it..

In Verilog, there is conditional compilation. You may look for it..

Good Luck..
Ilgaz

 

[FvM]

I agree with Ilgaz, that you should tell the purpose of omitting a module from synthesis.

As an additional remark, at worst case simply omitting the module instance can result in no logic synthesized for the top design.
If you are intending a kind of top town design (coding the lower modules later), you may want to insert a dummy module that
"consumes" input signals and generates output at the interface. Unfortunately, the dummy module implicitely constraints
the other module's timing, so the logic should be well considered.

 

[shitansh]

HI,

make use of define.v file

Reffer to attached file

if commnetout `define INCLUDE_MODULE_4 line in define.v module_5 will be synthesize else module_4 will besynsthesized

HTH
--
Shitansh Vaghela