Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

how to precharge dram bitline in hspice?

Status
Not open for further replies.

saeedgreat

Newbie level 4
Joined
Jan 9, 2021
Messages
6
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
112
hi. i'm simulating a dram in hspice and there is the read bit line that needs to be precharged before wordline read affects. the problem is i don't know how to precharge bitline .i saw some people use .ic for precharging sram bitlines and i tried that on dram but the voltage comes and goes after one nano seconds. i saw some papers that simulated this kind of dram in cadence using a pmos connected by gate to a precharge pulse and its source and drain connected to vdd and bitline.is it necessary in hspice too? why just not use a pulse?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top