AMSA84
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Hi guys. I have to design the layout of the above mentioned ota.
I am thinking on how layout the ota AMP. This OTA has PMOS input transistor.
What I was thinking to do was to follow the schematic. That is:
Interdigitize the cascode transistores that bias the diff. pair.
Interdgtz the differential pair.
Interdgtz the current mirror loads between them.
Interdgtz the upper current mirrors.
All this structured as in the schematic.
What you guys think?
Btw, all the transistors will havê the same width, so I will be using multiplicity of a lower transistor size.
I am thinking on how layout the ota AMP. This OTA has PMOS input transistor.
What I was thinking to do was to follow the schematic. That is:
Interdigitize the cascode transistores that bias the diff. pair.
Interdgtz the differential pair.
Interdgtz the current mirror loads between them.
Interdgtz the upper current mirrors.
All this structured as in the schematic.
What you guys think?
Btw, all the transistors will havê the same width, so I will be using multiplicity of a lower transistor size.