how to plano the floorplan of a OTA amplifier (3-current mirror OTA)

[AMSA84]

Hi guys. I have to design the layout of the above mentioned ota.

I am thinking on how layout the ota AMP. This OTA has PMOS input transistor.

What I was thinking to do was to follow the schematic. That is:

Interdigitize the cascode transistores that bias the diff. pair.

Interdgtz the differential pair.

Interdgtz the current mirror loads between them.

Interdgtz the upper current mirrors.

All this structured as in the schematic.

What you guys think?

Btw, all the transistors will havê the same width, so I will be using multiplicity of a lower transistor size.

 

[Dominik Przyborowski]

What is your input offset voltage obtained from monte carlo or hand calculation?
Sometimes drawing layout "as God commanded" is not worth of time and silicon area.

 

[AMSA84]

Offset is nota much important for this application.

 

[Dominik Przyborowski]

Offset is nota much important for this application.

So make it to minimize parasatic capacitances.

 

[AMSA84]

And what one should take into account to reduce the parasitic cap?