How to perform timing analysis of std cells

[IanKang]

Hi, I'm building (well, modifying actually) a .35 standard cell library.
Now I've built layout view, schematic view.
I've done DRC, LVS, and created abstract and LEF file by Abstract Generator.
I also extracted netlists from layout (LPE).

Now I'm stucked in creating timing library (.lib) which can be used by Synopsys.
Analysing timing cell by cell seem impossible.
Is there any tool I can generate .lib files from netlists I extrated?
Or is there any Hspice model I can use to perform timing analysis?

Thanks!

 

[carv_13]

This is a sample hspice file

$a sample hspice file
.include "your technology file"
.include lvstest.sp $ you should put your output file from extracion here

.option post
xi in out / inv $ Call your system to simulate. put I/O info first and then ends with subckt name

vdd! vdd! gnd 1.2V $ Your VDD voltage value
Vin in gnd pulse (0V 1.2V 0ns 100ps 100ps 1400ps 3000ps) $ How input varies during simulation
Cout_b out 0 20f $ output load
.tr 0.01ns 4ns $ simulation step and simulation time
.end $end your hspice

This is the one for inverter.

You can use the same for all other cells. I guess you would be wanting to analyze the worst case and best case scenarios for all the cells. Then you would have to sit to figure out the patterns that would help you to generate the best case and worst case scenarios and run the simulation in hspice.

-Aravind

 

[IanKang]

Thanks to Aravind,
Analyse basic logic gates is not a problem now.

But I still don't know how to deal with Flip Flops.
And I think I need pin capacitance as well.
Is there any model I can use?

Thanks a lot!

 

[carv_13]

For setup and hold you could try this



Total delay of the ff = T clk->q + setup time.

Hoping that helps.

-Aravind