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How to pass a (generic) parameter to different blocks?

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Hugo17

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I do have following block diagram which I would like to connect with a bus that use a generic parameter (adc). The blockdiagram looks like this:

block.png


The implementation for the file "block_name.vhd" is:

Code:
LIBRARY ieee;
USE ieee.std_logic_1164.all;


--  Entity Declaration

ENTITY block_name IS
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
GENERIC(width : INTEGER := adc);
PORT
(
gi_bus : OUT STD_LOGIC_VECTOR(width to 0)
);
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!

END block_name;


--  Architecture Body

ARCHITECTURE block_name_architecture OF block_name IS

BEGIN

END block_name_architecture;

Does someone know how to fix this problem?

Thanks!
 

shaiko

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Declare the block you want to instantiate as a component in your design.
 

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