how to partition or architecture?

[xworld2008]

I want to improve me skill in asic design, and i want to find some matter
to improve my ability about partition or archiecture.Can you tell me any
book or matter about partition or architecture, or what i should do?
Thanks.

 

[kelvin_sg]

Difficult to understand your question.
I think you can try to pick up a few working projects on
the www.opencores.org.

Kelvin

 

[ram]

Mainly you can partition the design on following basis -
1. Functionality
2. Reusability
3. Synthesis considerations
4. strength of team & expertise

Most of the times the design is partioned from functionality point of view.
For partitioning from synthsis point of view see the Synopsis DC training material aviliable in E-Book upload / download section

 

[FLEXcertifydll]

Yes, partition is based on you skill and knowing of you project. Timing and reuseable is importent.

 

[tom123]

1) Partition the design at functional boundaries.

2) Minimize the I/O connections between different partitions.

3) Register all inputs and outputs of each block. This makes logic
synchronous and avoids glitches and avoids any delay penalty on
signals that cross between partitions. Registering I/Os typically
eliminates the need to specify timing requirements for signals that
connect between different blocks.

4) Do not use “glue logic” or connection logic between hierarchical
blocks. When you preserve hierarchy boundaries, glue logic is not
merged with hierarchical blocks. Your synthesis software may
optimize glue logic separately, which can degrade synthesis results
and is not efficient when used with the LogicLock design
methodology.

5) Remember that logic is not synthesized or optimized across partition
boundaries, which means any constant values (signals set to GND,
for example) will not be propagated across partitions.

6) Do not use tri-state signals or bidirectional ports on hierarchical
boundaries. If you use boundary tri-states in a lower-level block,
synthesis pushes the tri-states through the hierarchy to the top-level
to take advantage of the tri-state drivers on the output pins of Altera
device. Because this requires optimizing through hierarchies,
lower-level boundary tri-state signals are not supported with a
block-level design methodology.

7) Limit clocks to one per block. Partitioning the design into clock
domains makes synthesis and timing analysis easier.

8) Place state machines in separate blocks to speed optimization and
provide greater encoding control.

9) Separate timing-critical functions from non-timing-critical functions.

10) Limit the critical timing path to one hierarchical block. You can
group the logic from several design blocks to ensure the critical path
resides in one block.

I want to improve me skill in asic design, and i want to find some matter
to improve my ability about partition or archiecture.Can you tell me any
book or matter about partition or architecture, or what i should do?
Thanks.

 

[kelvin_bao]

i have the same question,can somebody introduce some good books about this subject,thank you!

 

[jjww110]

reuse method book can give you some skill

 

[risccpu]

Here is summury from a training:
Partitioning is not just a functional issue. It can significantly affect the following process:��
Synthesis
Quality-of-Result (QOR)��
Synthesis constraints��
Synthesis scripts��
Synthesis compile time
Static timing analysis��
Floorplanning��
Layout

 

[alban]

how to partition the design
few solution for your question

 

[delay]

Do front-end and back-end partitions.

 

[salma ali bakr]

reuse methodology manual is a great book....go for it