How to overcome poly density error in layout

[Yathin P U]

Hi,

Please help me in solving this.

How do you overcome maximum poly density error?

Thanks in advance.

 

[lukden]

The easier way is make bigger space between device in layout.

 

[biggen5963]

Hi,

Please help me in solving this.

How do you overcome maximum poly density error?

Thanks in advance.

You could add spare poly/poly caps under the routing channels. You could increased poly compensation caps. You could add spare devices. You could add poly shielding under some critical lines and tie to GND.

 

[dick_freebird]

If your poly density is violating the max limit then adding more
won't help. But it would be unusual, other than in a bed of POP
caps or MOS caps, to see this happen. Unless the upper limit
is stupid low. And if you believe so, you might challenge the
foundry as to why. You'd think a flow would be decently
producible over a 10-90%, surely 20-80% fill range amd I am
used to seeing minimum density limits below 5% and usually
none for max, because it's practiclaly impossible to hit a max
density (in terms of producibility) in any sane useful circuit
layout. Other than maybe slabs of thick metal in power ICs,
and even there all I've seen is slotting rules, which in effect
set a max density of 90% or so (30um max metal, 5um slot,
as an example).

 

[biggen5963]

Ooo, I guess I read that wrong. I've never even seen a maximum density rule written in all of the processes I've worked in. Please disregard my previous message.

I'd be tempted to double check the calculation going on there before I did anything to the layout.