kimjin
Member level 3
vsim-3053
in my design ,i used a bidirection_bus,it's the type of inout,inout [3:0] data_bus;
in my testbench, i identified the signal:reg [3:0] data_bus;
but in the modelsim, it reports a error when i load the simulation program bidir_bus_test.v,the error said:
Error: (vsim-3053) E:/vhd/bidir_bus/bidir_bus_test.v(14): Illegal output or inout port connection (port 'data_bus').
# Region: /bidir_bus_test/u1
i'd wonder how to simulation the bidirection_bus,who can help me?
thank you.
in my design ,i used a bidirection_bus,it's the type of inout,inout [3:0] data_bus;
in my testbench, i identified the signal:reg [3:0] data_bus;
but in the modelsim, it reports a error when i load the simulation program bidir_bus_test.v,the error said:
Error: (vsim-3053) E:/vhd/bidir_bus/bidir_bus_test.v(14): Illegal output or inout port connection (port 'data_bus').
# Region: /bidir_bus_test/u1
i'd wonder how to simulation the bidirection_bus,who can help me?
thank you.