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How to model analog input for ADC in digital simulation

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wy21century

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Hi

I want to model a ADC in verilog and use it in digital simulation. My purpose is to make this behavior the same interface as the true analog one and use it in a digital SOC environment. Write some testbench to test its connection.

My problem is how to model the analog input because it is one bit width signal, how do I model the different input voltage level and convert it to a multi-bits digital output?
Can anyone with this experience help me?
 

avimit

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dude,
Your signle 'analog' type pin will somewhere be converted into multibit value inside your design. Its that multibit value point, that you will need to model.
I had done this before. Wot I did was, I wrote all the values of voltage/current values in a text file as 'float/real' values. Then I wrote a simle model in vhdl, which will read this text file, at a rate which is equal to your sample frequency, and then used this 'real' type value inside my design.
Hope it helps,
kr,
Avi
https://www.vlsiip.com
 

wy21century

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Good idea!

That is for VHDL. Unfortunately, we don't have similar way in verilog. So currently I am doing is using PWM code to simulate the analog input. We all know that PWM code is able to describe a multi level value by using different pulse width. Obviously, I wrote the behavior which can decode PWM as well.
 

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