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How to minimize the LDO voltage overshot?

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gekk

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when I simulate LDO in power on , the voltage overshot is very large. how can I minish the overshot? thanks!
 

LaszloF

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Re: LDO overshot

Most of the LDO's are very sensitive to the output filter capacitance ESR, if it's out of the interval, then instability occurs.
Try this: place an ideal capacitor in series with a 1Ohm resistor at the output, vary the resistor value until you don't have overshoot.
 

gekk

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Re: LDO overshot

i try , thanks!
 

ambreesh

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Re: LDO overshot

Firstwhat is the cause of the overshoot?
Assume you have removed the lood suddenly, the loop will take time to respond, which means your paas transistor is ON, it supplies charges till it is turned off.
These charges increase the voltage on our ouput cap.
Increasing the cap size can be one solution.
 

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